800G and 1.6T optical interconnect / silicon photonics / co-packaged optics technology and investment research

Technical bottleneck

• Bottleneck type: Capacity / qualification / packaging / testability
• Technical constraint: CPO and silicon photonics now hinge on design-for-test, fault detection, thermal co-design, and manufacturability rather than just raw device speed.
• Economic constraint: Hyperscaler qualification cycles and allocation discipline; new architectures need serviceability and standardization before broad deployment.

Adoption

• Driver: AI datacenter growth, 800G ramp, 1.6T transition, and packaging integration.
• Blocker: CPO timing shifts, thermal management, serviceability, and inventory/oversupply risk.

Product categories

800G/1.6T pluggable modules, silicon photonics PICs, lasers, co-packaged optics

Public companies exposed

COHR, LITE, CRDO, ANET, AVGO, MRVL, AAOI, AXTI

Validation signals

Coherent Q3 FY2026 revenue $1.81B +20.5% YoY and GAAP gross margin 37.7%; arXiv shows CPO still early but deployable; DFT work shows manufacturing/test issues are now first-order constraints.

Invalidation signals

If copper/AEC extends further or standardization/serviceability stalls CPO adoption.

Related product map rows

• LITE — Emerging: AI compute growth → 800G/1.6T optical interconnect demand → InP laser bottleneck → LITE dominant EML/laser supplier sold out through 2027; CPO delay extends pluggable runway · confidence low
• COHR — Emerging: 800G silicon photonics on full allocation; COHR EML lasers = critical component; CPO timing risk flagged (Semi Analysis Computex feedback) but thesis intact short-term · confidence low
• AXTI — Emerging: DIGITAL INFRA: InP substrate bottleneck for 400G/800G silicon photonics and defense/quantum applications; $632M capacity expansion confirms real demand; substrate for LiDAR/sensing also · confidence low
• ANET — Emerging: AI compute -> DC buildout -> networking bottleneck (800G/1.6T) · confidence low
• MRVL — Consensus: AI compute -> custom ASIC/silicon -> DC networking bottleneck · confidence low
• AVGO — Consensus: AI compute -> networking silicon bottleneck · confidence low
• AAOI — Early: AI compute -> DC buildout -> 800G/1.6T optics bottleneck · confidence low
• CRDO — Emerging: GPU scale-out → 800G/1.6T connectivity bottleneck (AEC active electrical cables) · confidence low
• CRDO — HiWire AEC Active Electrical Cables + optical DSP ICs: Signal retiming at 112/224 Gbps per lane in copper cables; DSP for coherent optical ZR/ZR+ · confidence high

Public companies exposed

• ANET (Arista Networks)
• COHR (Coherent)
• CLS (Celestica)
• LITE (Lumentum)
• JBL (Jabil)
• MXL (MaxLinear)
• SMTC (Semtech)
• AAOI (Applied Optoelectronics)
• AVGO (Broadcom)

Research Update — 2026-08-01

_Source: Celestica Q2 2026 10-Q + EX-99.1 earnings release during CLS deep-dive_

Technical readiness: deployed/scaling. 800G is in volume ramp inside hyperscaler CCS programs; 1.6T remains in qualification / early commercialization but is clearly part of customer roadmaps.

Key papers / sources:

• [SEC 10-Q] Celestica Q2 2026 10-Q (2026-07-27) — HPS revenue increased 58% YoY to about $1.9B in Q2 and 60% YoY to about $3.6B in 1H; communications revenue rose on hyperscaler networking demand; enterprise revenue rose on AI/ML compute ramp.
• [SEC EX-99.1] Celestica Q2 2026 earnings release (2026-07-27) — Q2 revenue and adjusted EPS beat guidance; FY2026 outlook raised; growth expected to accelerate in 2027.
• [SEC 10-Q] Same filing — top 10 customers were 83% of revenue; three CCS customers were 32% / 17% / 14% of Q2 revenue.

Bottleneck update: strengthened. The bottleneck has moved from pure optics spec to qualification / signal-integrity / power-delivery / thermal / test integration, and Celestica’s program mix shows that the market is still paying for the manufacturing layer that can pass that test.

Alternative/substitute risk: copper and AEC still pressure the pluggable runway, and if CPO standardization slips, some volume could stay in pluggables longer. That delays but does not remove the packaging/test bottleneck.

Timeline signal: 2027 growth acceleration suggests the 800G/1.6T transition is still early rather than saturated.

Adoption rate data: HPS plus 58% YoY in Q2 and 60% YoY in 1H; Communications revenue rose $242.6M sequentially on networking demand.

Thesis impact: demand-side validation improved. CLS is not just a downstream beneficiary; it is evidence that 800G/1.6T interconnect spending is still expanding and remains bottlenecked by qualified manufacturing capacity.

Why the bottleneck exists — science & engineering

• Afshar et al. "Enhancing Co-packaging Optics Enabled Silicon Photonics Security Assurance Hardware Fingerprinting." arXiv, 2026. CPO integration creates new failure modes: die-level hardware Trojans or process variations in the silicon photonics interposer can create side-channel leakage paths undetectable by standard electrical testing. The paper proposes optical-domain fingerprinting for CPO security assurance — validating that testability is now the primary CPO deployment constraint. [[arxiv] 2606.27612](https://arxiv.org/abs/2606.27612)
• Ahmed et al. "Design Considerations for Phase Modulation in Testable Photonic Systems and Co-packaged Optics." arXiv, 2026. Design-for-test (DFT) for photonic systems — the key engineering barrier to CPO volume deployment. Proposes on-chip phase modulators as built-in self-test structures to detect waveguide faults, thermal crosstalk, and laser degradation without external optical probing, addressing the serviceability problem that limits CPO adoption in hyperscaler data centers. [[arxiv] 2606.19674](https://arxiv.org/abs/2606.19674)
• Cheng et al. "A 1.6-Tbps Silicon Photonic Engine with Backside Attachment for Co-Packaged Optics." OFC 2024 Postdeadline Paper. Demonstrated the first complete 1.6T silicon photonic engine with flip-chip backside attachment to a switch ASIC — achieving <5 pJ/bit energy efficiency at 112 Gbps/lane. This is the manufacturing feasibility proof that moved CPO from lab to pre-production. [[doi] 10.1364/OFC.2024.Th4A.1](https://doi.org/10.1364/OFC.2024.Th4A.1)

Why it matters now — adoption & validation

• SEC Coherent Corp. 10-K FY2025 — Datacom revenue $2.4B (44% of total), 800G transceivers on full allocation through 2027; silicon photonics platform qualified at hyperscalers; 1.6T development progressing on schedule
• SEC Arista Networks 10-K FY2025 — Revenue $7.0B; 800G switch ports shipping at hyperscalers; 1.6T optics qualification underway; ANET's 800G/1.6T deployment cadence is the leading indicator for optical transceiver demand
• Industry OFC 2026 — Optical Fiber Communication Conference — CPO spotlight session: all major hyperscalers (Meta, Microsoft, Google) presenting CPO deployment roadmaps for 2027-2028; CPO moving from research to pre-production; pluggable 1.6T expected to ship at volume before CPO reaches production

Open questions

• [ ] Monitor CPO volume deployment timing — does it accelerate (bullish for silicon photonics suppliers) or slip (bullish for pluggable LRM like LITE/COHR)?
• [ ] Source primary revenue/backlog data for named companies

Backfill — differentiation_upgrade 2026-08-16

Backfill: differentiation_upgrade 2026-08-16

Public Parameter Table

Worked Calculation — cluster-level power saved by CPO

The CPO value proposition is a cluster-level power budget, not a module spec:

• 800G pluggable ≈ 14 W → 14 / 800 ≈ 17.5 pJ/bit [derived]
• 100K-GPU cluster × 800 Gbps = 80 Pbps; at 17.5 pJ/bit → 80e15 × 17.5e-12 ≈ 1.4 MW of optics power [derived]
• CPO at <5 pJ/bit → 80e15 × 5e-12 = 0.4 MW → ~1.0 MW saved per 100K-GPU cluster [derived]

~1 MW saved per 100K-GPU cluster — roughly the draw of a mid-size data hall — is the entire economic case for CPO. It is also why the real bottleneck has moved to testability/DFT (arXiv 2606.19674): a 1 MW-saving architecture that can't be field-serviced or fault-isolated never ships at hyperscale.

Sensitivity Analysis

• CPO reaches only 8 pJ/bit near-term → 0.64 MW → savings ~0.76 MW [derived]
• 1.6T pluggable at 25 W → 15.6 pJ/bit (slightly better than 800G) → the pluggable runway improves before CPO [derived]
• If copper/AEC (CRDO HiWire) extends reach to in-rack 800G, a slice of the optical budget stays electrical and the CPO TAM shrinks [derived]

Disconfirming Evidence

• CPO standardization/serviceability stalls: pluggables keep the volume; the <5 pJ/bit stays in the lab and the ~1 MW saving is never captured at scale.
• Copper/AEC reach extension: every meter AEC wins at 224 Gbps is a meter CPO loses.
• Oversupply/inventory risk: if hyperscaler allocation discipline eases, module ASPs compress and the energy-per-bit advantage is re-priced away.

Last Researched

2026-08-16