AI server 48V power delivery (multiphase VRM for GPU) technology and investment research

Technical bottleneck

• Bottleneck type: Efficiency / Density / Thermal / Phase current scaling
• Technical constraint: At 0.7V output and 3,500A load, I²R losses in PCB traces, connector pins, and inductor DCR must be <2% total to stay within thermal budget. A 100-phase VRM at 2 MHz switching frequency requires careful phase-interleaving to avoid beat frequencies and EMI. Transient response: when the GPU jumps from idle (50A) to full load (3,500A) in <1 µs, the VRM must respond without voltage droop exceeding ±3% (21 mV at 0.7V) — or the GPU crashes.
• Economic constraint: MPWR's proprietary BCD (Bipolar-CMOS-DMOS) process integrates high-voltage DMOS power devices with precision CMOS control on one die. Competing with discrete solutions on efficiency, density, and cost requires process-level integration taking years to develop.

Adoption

• Driver: GPU power scaling (700W H100 → 1,500W Rubin → 2,500W Rubin Ultra); 48V bus adoption reducing I²R losses 16× vs 12V; phase count and VRM content per GPU growing 4x
• Blocker: 800V DC rack architecture may bypass 48V intermediate bus; GaN power stages could reduce phase count; Chinese DrMOS competitors (JWIT) gaining share

Public companies exposed

MPWR (Monolithic Power — multiphase controllers, DrMOS, 48V DC-DC converters), VICR (Vicor — power modules, factorized power architecture), ON (onsemi — DrMOS, smart power stages), Infineon (DrMOS, power stages), Renesas (multiphase controllers)

Validation signals

• MPWR data center revenue growing rapidly; proprietary BCD process moat
• VICR 48V/800V power modules designed into AI server reference architectures
• Phase count 4x from H100 to Rubin Ultra (analyst GPU teardowns)
• Chinese DrMOS competitor JWIT accelerating but MPWR/VICR still dominant in high-end

Backfill — differentiation_upgrade 2026-08-16

Backfill: differentiation_upgrade 2026-08-16

Public Parameter Table

Worked Calculation — VRM attach rate and bus-voltage physics

Two numbers bracket the opportunity:

1. Attach rate: 72 GPUs × ($100–280) = $7.2K–20K of VRM silicon per NVL72 rack, growing ~4× from H100 to Rubin Ultra as phase count scales with GPU power [derived].
2. Bus physics: I = P/V. A 100 kW rack is ~8,333 A at 12V vs ~2,083 A at 48V. Since I²R ∝ I², moving to 48V cuts distribution loss by (1/4)² = 16× — and copper cross-section (∝ I) drops 4×. There is no physics alternative: at rack power >50 kW the 48V bus is mandatory [derived].

This is the purest "picks-and-shovels" position in the physical-AI stack: VRM silicon attaches to every GPU regardless of which vendor wins, and its content grows with GPU power.

Sensitivity Analysis

• GPU power 1,500 W (Rubin) vs 2,500 W (Ultra) → phase count ~60–84 vs ~100–140 → VRM silicon ~$60–170/GPU [derived]
• 800V DC rack (I²R 278× vs 48V) → the 48V intermediate bus is bypassed → MPWR/VICR's 48V layer is the one at risk [derived]
• GaN power stages at >95% efficiency → fewer phases needed → VRM silicon per GPU compresses [derived]

Disconfirming Evidence

• 800V DC adoption: bypasses the 48V layer entirely — the note's own open question, and the single largest threat to the 48V VRM thesis.
• GaN reducing phase count: higher per-phase current (GaN HEMTs) means fewer phases per GPU → lower attach rate.
• Chinese DrMOS (JWIT) commoditization: price erosion at the exact time content is growing.

Last Researched

2026-08-16