High-bandwidth memory (HBM) — HBM3E and HBM4 technology and investment research

Technical bottleneck

• Bottleneck type: Capacity / 3D stacking yield
• Technical constraint: TSV formation through 8-12 DRAM die layers with <5 μm diameter and >50:1 aspect ratio; microbump interconnect at 40-55 μm pitch requiring <2 μm alignment; thermal management of >16 GB stacks consuming 5-7W per stack — heat must travel through silicon interposer to substrate
• Economic constraint: SK Hynix dominates HBM3E (>90% share); Samsung and Micron are ramping but 6-12 months behind; HBM wafer consumption is 2-3× DRAM wafer equivalent per GB; HBM capacity is committed years in advance to NVIDIA and AMD — effectively pre-sold supply

Adoption

• Driver: NVIDIA B200/B100 (8 stacks of 8-Hi HBM3E per GPU, 192-288 GB); AMD MI300X (8 stacks of 8-Hi HBM3); custom ASICs (AWS Trainium, Google TPU) also adopting HBM; HBM4 with 2048-bit interface for 2026-2027
• Blocker: Hynix HBM capacity expansion timeline (fabs take 2-3 years); Samsung HBM3E qualification delays; advanced packaging (CoWoS) co-bottleneck — HBM supply without CoWoS capacity does not deliver complete systems; HBM4 transition might reset qualification cycles

Public companies exposed

MU (Micron — HBM3E ramping

HBM4 in development)

NVDA (NVIDIA — primary consumer

drives allocation)

AMD (MI300X — second-largest consumer)

AVGO (Broadcom — custom ASIC HBM integration)

QCOM (Qualcomm — AI PC with HBM?)

Validation signals

MU HBM revenue guidance and capacity commitments; SK Hynix/Hynix HBM3E capacity expansion announcements; HBM lead times extending past 52 weeks; HBM pricing (premium over commodity DRAM) widening

Invalidation signals

HBM supply catching up to GPU demand (lead times normalizing); Samsung gaining >20% HBM3E share from Hynix; alternative memory technologies (GDDR7, LPDDR6 on interposer) offering near-HBM bandwidth at lower cost

Related product map rows

• ANET — Emerging: HBM-driven GPU cluster expansion increases scale-out fabric demand; Arista is a second-order beneficiary, not an HBM supplier · confidence low

Research Update — 2026-07-18

_Source: Micron Q3 FY2026 earnings release during MU deep-dive_

Technical readiness: deployed / scaling; Micron says HBM4 is already in high-volume shipments and HBM4E volume production is expected in calendar 2027.

Key papers / sources:

• SEC 8-K EX-99.1 — Q3 FY2026 revenue $41.46B, GAAP gross margin 84.6%, operating margin 80.4%; HBM4 high-volume shipments; samples to multiple end-customers.
• StockAnalysis financials — FY2025 revenue $37.38B (+48.9% YoY), gross margin 39.8%, operating margin 26.1%.

Bottleneck update: strengthened; the release shows the HBM scarcity regime is still translating into very high margins and forward visibility.

Alternative/substitute risk: unchanged; the release does not remove the longer-term risk from Samsung/SK Hynix execution or lower-bandwidth substitutes.

Timeline signal: HBM4E volume production is expected in calendar 2027, keeping qualification and ramp risk live over the next several quarters.

Adoption rate data: HBM4 is already in high-volume shipments for a lead customer's platform; qualification samples have been shipped to multiple end-customers.

Thesis impact: reinforces HBM as a binding bottleneck for AI accelerators and validates Micron as a scaled US supply node in the AI Factory layer.

Research Update — 2026-07-26

_Source: ANET Q1 FY2026 filing/companyfacts + existing HBM source ladder_

Technical readiness: deployed / scaling; HBM4 is in high-volume shipments, and HBM4E volume production is expected in calendar 2027.

Key sources:

• SEC companyfacts — Arista Networks — FY2025 revenue $9.006B, Q1 2026 revenue $2.709B; annualized Q1 revenue run-rate is $10.836B, or 20.3% above FY2025 revenue.
• SEC EX-99.1 — Arista earnings release — XPO high-density liquid-cooled pluggable optics reduce networking racks by up to 75% and save up to 44% of floor space versus traditional pluggables; 2026 NPS score 89 with 94% strongly positive.
• JEDEC JESD235D — HBM3E uses a 1024-bit interface, 8-12 die layers, and >1 TB/s per stack.
• SEC 8-K EX-99.1 — Micron — HBM4 high-volume shipments; HBM4E volume production expected in calendar 2027.

Public parameter table:

• HBM3E interface width: 1024-bit
• HBM4 interface width: 2048-bit
• HBM4 vs HBM3E interface width: 2.0x
• HBM3E bandwidth: >1 TB/s per stack
• HBM4 bandwidth: >1.5 TB/s per stack
• HBM stacks per high-end GPU: 8
• ANET FY2025 revenue: $9.006B
• ANET Q1 FY2026 revenue: $2.709B
• XPO rack reduction: up to 75%
• XPO floor-space reduction: up to 44%

Worked calculation:

• HBM4 interface step-up = 2048 / 1024 = 2.0x, so the next-generation spec doubles bus width before any further bandwidth uplift.
• ANET Q1 annualized run-rate = 4 × $2.709B = $10.836B, which is $1.830B above FY2025 revenue; premium = $1.830B / $9.006B = 20.3%.
• XPO floor-space savings as a fraction of rack-count reduction = 44 / 75 = 0.59, indicating serviceability/thermal overhead still consumes meaningful footprint even as rack count collapses.

Bottleneck update: unchanged to strengthened. HBM remains the binding memory bottleneck, and dense AI clusters are layering a second bottleneck on top of it: networking/serviceability.

Sensitivity analysis:

• If HBM4E volume production lands in 2027 as guided, scarcity likely persists through the next 2-4 quarters.
• If monolithic 3D DRAM or tiered DRAM architectures deliver 3-5x capacity at acceptable bandwidth, HBM's moat weakens.
• If the effective HBM4 bandwidth step-up slips, the scarcity window extends for suppliers but delays downstream cluster scaling.

Alternative / substitute risk: tiered or monolithic 3D-DRAM approaches, or other higher-capacity memory architectures, could undercut HBM if they exit the lab and qualify economically.

Timeline signal: HBM4 is already in high-volume shipments; HBM4E is the next checkpoint in 2027.

Adoption rate data: JEDEC's 2048-bit HBM4 standard plus Micron's production cadence indicate the ecosystem is now in scaling rather than R&D.

Thesis impact: HBM remains the memory bottleneck for AI accelerators; ANET is a second-order demand-side beneficiary because HBM-constrained GPU shipments still require the networking fabric to scale.