Silicon carbide (SiC) substrates and epitaxy technology and investment research

Technical bottleneck

• Bottleneck type: Yield / Capacity / Crystal growth
• Technical constraint: Bulk SiC crystal growth (PVT method) has 100× slower growth rate than silicon; basal plane dislocations, micropipes, and stacking faults reduce device yield; 200mm transition is >5 years behind silicon
• Economic constraint: Wolfspeed capacity buildout balance-sheet overhang; Chinese SiC substrate oversupply risk; $1B+ capex per 200mm wafer fab; substrate cost is 30-50% of device cost

Adoption

• Driver: EV inverter adoption driving volume; 800V architectures require SiC; industrial motor drive efficiency regulations; renewable inverter demand
• Blocker: IGBT performance improvement at lower voltages; GaN encroachment at <650V; Chinese substrate price collapse if oversupply materializes

Public companies exposed

WOLF

STM

ON

NXPI

COHR

Validation signals

WOLF Mohawk Valley utilization ramp; 200mm device qualification announcements at OEMs; SiC design wins for >800V industrial drives

Invalidation signals

WOLF liquidity/bankruptcy risk; Chinese 200mm SiC capacity exceeding global demand; GaN-on-Si achieving 1200V capability

Public companies exposed

• WOLF (Wolfspeed)
• ON (ON Semiconductor)
• STM (STMicroelectronics)
• COHR (Coherent)
• IFNNY (Infineon Technologies)

Backfill — differentiation_upgrade 2026-08-16

Backfill: differentiation_upgrade 2026-08-16

Public Parameter Table

Worked Calculation — furnace-week throughput bottleneck

The binding constraint is crystal-growth throughput, not demand. At a representative 0.3 mm/hr PVT growth rate:

• usable boule length = 25 mm → 25 / 0.3 ≈ 83 hr ≈ 3.5 days per boule [derived]
• boules per furnace-week ≈ 2 → at ~50 usable 150mm wafers/boule (25 mm ÷ 0.35 mm slice ≈ 71, less kerf + polish loss) → ~100 wafers per furnace-week [derived]
• Silicon at ~60–90 mm/hr grows the same 25 mm in ~17–25 min — a ~100–300× growth-rate gap that is the root of the entire substrate bottleneck [derived]

This is why SiC capacity is measured in furnace count and why WOLF's >$1B 200mm buildout is capex-intensive while yielding wafer counts that are a rounding error next to silicon.

Sensitivity Analysis

• Growth rate 0.1 mm/hr (defect-minimizing end) → 250 hr/boule → ~0.67 boules/furnace-week → ~34 wafers/week [derived]
• Growth rate 1.0 mm/hr (aggressive) → 25 hr/boule → ~6.7 boules/furnace-week → ~336 wafers/week [derived]
• Substrate share 30% vs 50% of device cost → ~2× swing in the addressable substrate TAM at fixed device demand [derived]

Disconfirming Evidence

• Chinese substrate oversupply (TankeBlue / SICC): if 150mm (and eventually 200mm) substrate ASPs collapse on Chinese capacity, the bottleneck migrates from "can we grow it" to "can we qualify the device" — WOLF's vertical integration flips from moat to stranded-cost liability.
• GaN-on-Si reaching 1,200V: erodes SiC's voltage advantage from below; the 650–1,200V sweet spot is exactly where the volume is.
• IGBT improvement (7th-gen trench field-stop): narrows the efficiency gap in the 1.2kV motor-drive segment, shrinking the TAM SiC must win.

Last Researched

2026-08-16